CSCI 361


Computer Architecture

3 Cr. (Hrs.:3 Lec.)

Studies the design and organization of computer systems, including the instruction set and interconnection of hardware components. Topics include computer performance, assembly language programming, microprocessor architecture, pipeline processing, memory and storage organization, and multiprocessor computers. Prerequisite: CSCI 255 (2nd)

Course generally offered spring (2nd) semester.

Expectations:

E1. Students understand at a high-level how a computer processor operates (fetch-and-execute cycle, interrupts, registers, memory, addressing, etc.) (CSCI 255, R1)

E2. Students know and can use numbers in any base and can convert numbers between bases. (CSCI 255, R2)

E3. Students know who to design, write, debug and test assembly and high-level language programs in a structured, modular, and well-documented manner. (CSCI 255, CSCI 232)

Course Outcomes:

R1. Students are familiar with historical developments in computer hardware and associated performance improvements.

R2. Students know how to evaluate hardware performance and are able to choose the best system or hardware design given a set of alternatives. (CAC-c, j; EAC-c, e)

R3. Students know the instruction set, for a specific architecture, including the different instruction formats, addressing modes and relationships to higher languages. (CAC-c: EAC-1)

R4. Students understand how procedures, pointers and arrays are implemented in assembly and machine code. (CAC-c; EAC-1)

R5. Students know the characteristics of a good instruction set. (CAC-c, j; EAC-1)

R6. Students can design and implement an assembler (CAC-c, i, k; EAC-e, 1)

R7. Students can research and present a recent computer architecture/system not covered in lecture. (CAC-f; EAC-g, j)

R8. Students understand how arithmetic and logic operations are designed and implemented. (CAC-a, c; EAC-a, c)

R9. Students understand single cycle and pipelined datapaths and can modify either to implement additional MIPS instructions. (CAC-c, j; EAC-c, e)

R10. Students understand pipelining, its associated hazards and techniques to best handle hazards. (CAC-c, j; EAC-c, e)

R11. Students understand memory hierarchy, basics of caches, system buses, and how they affect computer performance. (CAC-c; EAC-c, e)

R12. Students are familiar with different multiprocessor architectures. (CAC-c; EAC-c, e)